ECL gates, switches or circuits generally include a pair of transistors providing alternative transistor collector paths from a high potential line voltage V.sub.cc at ground or zero volts. The transistors are operatively coupled with a common emitter coupling for switching current between the collector paths according to input signals at the base of one of the transistors designated the input transistor. A current source V.sub.cs is coupled between the common emitter coupling and a negative potential V.sub.ee at, for example, -5.2 volts +0.5 volts, for generating current in the alternate transistor collector paths.
The input transistor receives ECL input data signals at the base of the input transistor. The other transistor constitutes a reference transistor and a negative reference voltage V.sub.bb typically in the range of -1.2 to -2.0 volts is applied to the base of the reference transistor to establish the relative level of the high and low level data signals in the negative voltage range. The output of the ECL gate, switch or circuit is obtained from the collector nodes of the ECL transistors typically through emitter follower buffer transistors which provide current gain and shift the voltage levels.
The voltage sources for the reference volta V.sub.bb and the ECL current source voltage V.sub.cs are generally provided by a separate bias generator or bias voltage source for operation of the ECL circuit in the selected negative voltage range. For example, the reference voltage V.sub.bb is typically selected to be in the range of -1.2 to -2.0 volts. The high level or logic "1" data signals are therefore typically in the range of -0.8 to -1.6 volts while the low level or logic "0" data signals are for example in the range of -1.6 to -2.4 volts according to the selected value of the reference voltage V.sub.bb. The ECL current generator or current source V.sub.cs is preferably compensated so that the ECL gate or switch can operate despite variations of the line voltage source V.sub.cc.
A prior art voltage compensated bias generator or voltage source for the reference voltage V.sub.bb and the current source V.sub.cs is illustrated in FIG. 1. Shunt regulator transistor Q3 stabilizes the output voltage for the current source voltage V.sub.cs and reference voltage V.sub.bb. The current source voltage V.sub.cs may be tied to the emitter of either output transistor Q5 or output transistor Q6. The collector current in transistor Q5 together with resistor R5 establishes the voltage level of reference voltage V.sub.bb while buffer transistor Q7 buffers the reference voltage source V.sub.bb to provide a low impedance source.
Similarly, the current source voltage V.sub.cs is a low impedance source buffered by either transistors Q5 or Q6. The level of the current source voltage V.sub.cs is set by resistor R3 and related components as hereafter described.
The base collector shorted transistor Q8, base resistor R7, transistor Q4 and emitter resistor R4 establish the collector current I.sub.C Q4 through transistor Q4. The collector current I.sub.C Q4, plus the current I.sub.RT through temperature dependence resistance R.sub.T plus the base current I.sub.B Q3 through shunt regulator transistor Q3 set the voltage drop across resistor R3. The voltage level of current source V.sub.cs is therefore set by the voltage dro V.sub.R3 across resistor R3 and the voltage drop V.sub.BE Q3 across the base emitter junction of shunt regulator transistor Q3.
By this circuit coupling arrangement the voltage level of current source voltage V.sub.cs tends to be stabilized because for example if V.sub.cs begins to fall the base drive to shunt regulator transistor Q3 decreases, the collector current I.sub.C Q3 decreases, and the base potential of transistor Q5 rises tending to stabilize the current source voltage V.sub.cs. In conventional bias generators for ECL circuits however the collector current of shunt regulator transistor Q3 is subject to variation from variations in the line voltage V.sub.cc. This will result in undesirable variations in the bias generator outputs V.sub.bb and V.sub.cs due largely to changes in the base emitter potential of transistor Q3. For high performance ECL circuits, voltage compensation in response to variations of the line voltage V.sub.cc for regulating the shunt regulator transistor collector current I.sub.C Q3 is accomplished by an active collector load circuit which conventionally incorporates a PNP-type transistor Q9 in the collector circuit of shunt regulator transistor Q3. The collector current of transistor Q3 is set by the base emitter potential of transistor Q9 and resistor R6 and is only logarithmically dependent upon the line voltage Vcc.
A disadvantage of the conventional active collector load circuit is that high performance ECL circuits are generally fabricated with an all NPN bipolar process and it is difficult to fabricate a PNP-type transistor in such a process. Furthermore, the active collector load circuit itself introduces temperature variation problems while compensating for variations in the power supply line voltage V.sub.cc. In particular, the output voltage sources V.sub.bb and V.sub.cs exhibit a significantly non-uniform rate of change with temperature, thus restricting the operating temperature range of high performance ECL circuits.
As illustrated in the graph of FIG. 2, in the conventional prior art bias generator, as the temperature increases, the V.sub.BE 's of the respective transistors decrease while the resistances of the various resistors increase thereby reducing the collector current I.sub.C Q3 of the shunt regulator transistor. As the device cools down the potential drop V.sub.BE across the base emitter junctions of the transistors increases while the resistances of the respective resistors decrease thereby increasing the collector current I.sub.C Q3. It is this temperature variation in the shunt regulator transistor collector current I.sub.C Q3 introduced by the conventional active collector load circuit that produces undesirable variations in the reference voltage output V.sub.bb and the current source voltage output V.sub.cs affecting the operation of ECL gates, switches and circuits serviced by the bias generator voltage source.
The operating temperature range of the conventional bias generator and associated ECL circuits is substantially limited. A linear variation of the output voltage source V.sub.bb with temperature is most desirable. However, the active collector load causes significant non-linearity in the variation of the output voltage source V.sub.bb with temperature as illustrated in FIG. 3. A disadvantage of the prior art limitation is that the circuits are not adequate for the broader operating temperature ranges of for example -55.degree. C. to +175.degree. C. required in many applications.